Hi.
I am confused a bit about the solution for 2:4 decoder in the picture below.
Please help me with the question in the figure.
Thanks.

 

You are both correct.

Notice that the author has chosen a solution such that the exact same transistor layout can be used for all four channels with just the signal connections being different. There is some utility in that because it might make their standard cell library more compact. But it costs them space (6 transistors instead of 4 per channel) and speed (twice the propagation delay). Everything's a tradeoff.

 

Notice that the author has chosen a solution such that the exact same transistor layout can be used for all four channels with just the signal connections being different.

With my layout, all four channels are also the same. They are all NOR gates, exactly the same, just different input signals.

 

With my layout, all four channels are also the same. They are all NOR gates, exactly the same, just different input signals.

You're right. I was thinking in my mind of the case where you don't have the complemented input signals available. That being the case, I don't know why the author does it the way they do except possibly to use a strong inverter to drive long lines and/or lots of gates. That's probably the reason.