16F88 external Vref setup?

Discussion in 'Embedded Systems and Microcontrollers' started by tracecom, Jan 1, 2014.

  1. tracecom

    Thread Starter AAC Fanatic!

    Apr 16, 2010
    3,871
    1,394
    I have the test circuit in the attached schematic working, including the LCD. All it does is read VR1 and VR2, display the readings on the LCD, and light an LED corresponding to whichever pot is set higher. I want to add my external Vref source to it.

    If I change PortA.3 to analog in ANSEL, connect the positive side of my external 4.096V reference to PortA.3, connect the negative side to ground, and change bits 5-4 in ADCON1 to 10, are there any other changes I must make to use the external Vref?

    Thanks.
     
  2. JohnInTX

    Moderator

    Jun 26, 2012
    2,348
    1,029
    Looks right. Be sure to set TRISA.3 to 1 (input) as well. Consider strapping the unused IO pins with resistors or set them to output 0.

    Other than that, looks good to me.
     
    tracecom likes this.
  3. tracecom

    Thread Starter AAC Fanatic!

    Apr 16, 2010
    3,871
    1,394
    When I adjust VR1 or VR2 to yield a digital value of 512, my DMM measures the wiper of the pot at 2.052V; I think that confirms that my Vref of 4.096V is being used. Correct?
     
  4. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,395
    1,607
    Yep, looks good to me.

    All I see is your pots can adjust up to 5V so they go above the Vref. Once they equal the reference the conversion reads the max.
     
  5. tracecom

    Thread Starter AAC Fanatic!

    Apr 16, 2010
    3,871
    1,394
    Yes, I just tested that. The digital reading maxes out at 1023, and further increases in voltage don't change the digital reading. I have noticed that if I am turning VR1, the digital reading maxes out, and when I continue turning the pot, eventually there is a change in the digital reading for VR2. I don't understand that, but it is repeatable.

    I suppose I could pad the high side of the pots to prevent them from going over 5V.

    Thanks.
     
  6. JohnInTX

    Moderator

    Jun 26, 2012
    2,348
    1,029
    Frequently, the pots (and other analog sources) are driven by Vref buffered somehow (voltage follower op amp etc). That way, power supply drift affecting Vin_max, padding resistor tempcos, Vref tolerances etc. won't affect the ADC scaling.

    As ErnieM pointed out (and I didn't think to) ADC readings are defined and limited by the range of Vref + and - so anything out of that range will be problematic.

    The spilliage of the overdriven signal into the other channel is likely caused by overcharging the sample/hold capacitor. Its not getting enough time to settle after channel change before the conversion starts. A reasonable approach is to detect both 000h and 3FFh (min / max ADC result) and define those as under/overflows and flag as errors. That will at least alert the firmware to potential out-of-tolerance readings on other channels as well as flag bad sensors, broken circuits etc. on the channel being read.

    Sounds like you are on the right track, though.
     
    tracecom likes this.
Loading...