16bit * 16bit multiplier

Discussion in 'Homework Help' started by simon0123, Feb 25, 2010.

  1. simon0123

    Thread Starter New Member

    Feb 25, 2010
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    0
    i am designing a 16bit * 16bit multiplier by using Radix 4 algorithm. The structure required is pipeline structure. i want to know how to design a circuit to perform 2 bit left shifting which is used to control multiplexer output.
    Can anyone teach me how to design a 2 bit left shifting ciruit.
     
  2. Papabravo

    Expert

    Feb 24, 2006
    10,179
    1,800
    Consider two registers in your pileline, each of length n-bits. Register A is before Register B, and you want Register B to be equal to the value in Register A shifted left by two bits. A(0),...,A(n-1) are the outputs of register A and dB(0),...,dB(n-1) are the inputs of Register B. Wire the inputs of register B as follows:
    Code ( (Unknown Language)):
    1.  
    2. dB(0) = 0 ;
    3. dB(1) = 0 ;
    4. dB(2) = A(0) ;
    5. dB(m) = A(m-2) ; for m in {3,...,n-1}
    6.  
    After every clock cycle the output of Register B will be equal to the value in Register A shifted left by two bits. I have no clue what you want to do with bits A(n-1) and A(n-2). In this scheme they have nowhere to go.
     
  3. simon0123

    Thread Starter New Member

    Feb 25, 2010
    2
    0
    sorry , i make a mistake, it should be shifted to right instead of left
    but how can i implement it by using hardware? eg DFF , LGOIC GATE
     
    Last edited: Feb 25, 2010
  4. Papabravo

    Expert

    Feb 24, 2006
    10,179
    1,800
    I told you how to do it using hardware. If you want to shift to the right, you wire the two registers as follows:
    Code ( (Unknown Language)):
    1.  
    2. discard A(0) ;
    3. discard A(1)
    4. dB(0)   = A(2) ;
    5. dB(1)   = A(3) ;
    6. dB(n-3) = A(n-1)
    7. dB(n-2) = 0 ;
    8. dB(n-1) = 0 ;
    9.  
    You do understand what I just described -- don't you?
     
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