16-bit synchronous binary counter

Discussion in 'Homework Help' started by mikez, Jan 29, 2013.

  1. mikez

    Thread Starter Member

    Jan 21, 2013
    47
    0
    Hi all,
    I have been given the task of creating a 16-bit synchronous counter out of two 3-bit, and two 5-bit counters. I have started the initial process of getting my circuit down on paper before I go off and get frustrated with the wonderful piece of software known as Xilinx. I have a quick question though. In the instructions it specifies to use a CLK and CE (I believe this was "clock enable" input) in my design. I would then have my Terminal Count as an output that would then be ANDed with the CE of my next counter in series. Now here is my question: Am I going to want to connect the CLK and CE both to the same input? But have my CE in my other counters (not my first one in series) ANDed with my Terminal Count coming from the first adder?
     
  2. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    CE means Chip Enable. In most ICs, this is an input that lets you select whether you want the IC to operate or not, regardless of its other inputs and clock.
    When the chip is disabled, it might output a constant LOW, highZ or simply hold its state, depending on the IC. Datasheets specify the behaviour in each case.
    You may find the CE pin labeled as G in some cases.
    Google some counter datasheets and see how the CE pin operates.

    There are two ways to interpret your specifications.

    The first is to assume that the counters you have in your hands are nothing more than an array of Flip Flops and you have to implement teh CLK and CE pins in your final design, in some way.

    The other is to assume that you have two 3-bit and two 5-bit virtual complete counters, with CLK and CE pins available on each one.

    Those two cases require a different approach. Try to come down to which one applies in your case and we can talk more about it.
     
  3. WBahn

    Moderator

    Mar 31, 2012
    17,788
    4,807
    And to follow up on another thing you said regarding connecting CLK and CE to the same input. This is pretty much NEVER what you want to do. In almost all chips, all of th other inputs need to be stable when the CLK signal makes its active transition (generally the rising edge). If any of the other inputs change, including asynchronous reset inputs, the results are unpredictable. The period during which the other inputs must be stable is known as the "setup and hold time" window. It may be different for different inputs. When you are designing a circuit one approach is to look at the data sheet for the maximum size of this window for any input and then double it and use that for all inputs. If that crowds your design, then either find a faster part or, if necessary, reduce your margins and even treat the different pins differently. But if you are pushing the specs that hard, you better know what you are doing.
     
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