12 stage binary ripple counter

Discussion in 'General Electronics Chat' started by blue6x, Apr 25, 2005.

  1. blue6x

    Thread Starter Active Member

    Apr 6, 2005
    38
    0
    can someone help me explain clerly how this 12 stge binry counter timing diagram works? Thanks for you guys...

    Its a bit confusing to me....
     
  2. pebe

    AAC Fanatic!

    Oct 11, 2004
    628
    3
    Hi blue,
    This binary counter chip contains 12 bistables (flipflops), so called because they have 2 steady states. Each flipflop drives the next like this.

    Look at Fig.5 on page 4. The two inverting buffers on the left take in control signals.
    The pin marked CP is the clock pulse input. The bar above the letters CP indicate that clocking occurs when the pin goes low. The MR pin is the master reset. You can see it connects to all the FF’s. There is no bar above MR so it is active when the pin is high. When MR is high all R0’s will be low and all the FFs will be reset, so each will have low at its barQ (again, the bar indicates it is normally low). The Q pins on each FF will be high and the pins Q0 to Q12 will all be low. These last outputs give the binary count so the count in the reset condition will be zero.

    Q0 is the ‘units’ or ‘1’s count. Q1 is the ‘2’s count. Q2 is the ‘4’s.Q3 is the ‘8’s count… and so on. In binary, the units count (Least Significant Bit) is always printed at the right hand side so 001 is 1, and 110 is six.

    Each time a clock pulse arrives FF1 will change state, ie. toggle. Qlow will change to Qhigh and visa versa. BarQ will always be the opposite of Q

    To make the chip operate, the reset MR must be taken low, else CP will have no effect (see the function table). So take CP high and MR low. Now we are ready to count.

    A negative pulse of CP will now be inverted and the take T of FF1 high. That ‘flips’ the FF into its second state and puts barQ low. Note that barQ is connected to T of FF2, so that goes high. Q is always the opposite of barQ so Q is low.
    Through the inverter, Q low makes Q0 go high. That gives a count of 1. That is the units or ‘1’s count = 000000000001
    The pulse at CP ends so CP goes high again. That does not affect the counter at all. Now for the next count.

    The next CP pulse will flip FF1 back to its reset state and Q0 will go low again to give a 0. BarQ goes high and takes T of FF2 high. That flips FF2 and Q1 goes high to give a count of 2 = 000000000010

    The process now repeats for the next count to give = 000000000011 = 3. You can see that every time a FF changes state twice, it changes the next stage once to give a binary count.

    The timing diagram Fig 6 shows the state of the pins during the counting process. Although it is correct, it has been squashed to get it onto the page and large sections are left out where spaces are shown. Try to visualise it where there are many cycles of a square wave at Q0, and half that number for Q1 and half again for Q2 and so on.

    I hope that may help.
     
  3. blue6x

    Thread Starter Active Member

    Apr 6, 2005
    38
    0
    thanks, i'm looking at it now.
     
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