I have a slave clock which requires a pulse every second of alternating polarity. I also have an unfinished project using several dividers which is giving me a +ve going 1 second pulse but I have stalled at the output stage.

Now I have gone off at a tangent after stripping down one of those mechanisms that form the basis for nearly all cheap quartz clocks and found, at its heart, a pcb that is outputting such a pulse from a pcb only about 1 cm square ! (pic attached)

The pulse is 12ms and ± 0.6v with dc at half the AA battery voltage. The clock needs ± 4v at 220ma to step the motor. I don't think I could use a bipolar output stage (barely enough volts and not enough current) or a fet because not enough voltage. I can only think op amps. I can design a circuit working from a ± 5v supply which does one polarity pulse (+) but not how to get a neg pulse from the other op amp from the same input.
The question is, is the op amp solution the way the go or is there a better way. Any thoughts appreciated..

 

How about a good old 4060 with a cheap tuning fork 32768Hz crystal? That can give an output of 2Hz, if I remember right. Another divider? The +/- supplies can go as + and ground to the chip. This can drive a high current op-amp buffer powered by +/- supply.

 

a pulse every second of alternating polarity.

Do you mean a pos pulse, then 1 sec later a neg pulse, then 1 sec later a pos pulse ..... Or do both pos and neg pulses occur within a single 1 sec time-frame?

 

The 1.5V desk clocks output two pulsed at 2 second intervals, 180° apart. If you diode-OR them you get a one pulse per second. Some have outputs that are pull-ups and some as pull-downs (attached I have used). In your case I would not OR them, but take the two outputs to separate transistors. You didn't say what pulse length the clock requires, but you may need to follow this with two monostables to lengthen the pulses. Then use these to drive an H-bridge.

Hen

 

How about a good old 4060 with a cheap tuning fork 32768Hz crystal? That can give an output of 2Hz, if I remember right. Another divider? The +/- supplies can go as + and ground to the chip. This can drive a high current op-amp buffer powered by +/- supply.

The attraction of this tiny circuit was that is already running a 32768Khz crystal and the tiny surface mount divider is doing exactly what I need - except for the voltage level and quite possibly the pulse width.

The original "motor" seems to have a 100 ohm coil so that's why you can see a 100 ohm resistor in the jpeg.

Alec..Yes...this type of motor needs a + pulse, then 1 sec later a neg pulse....and so on.

(QUOTE)...Hen .. The 1.5V desk clocks output two pulsed at 2 second intervals, 180° apart. If you diode-OR them you get a one pulse per second. Some have outputs that are pull-ups and some as pull-downs (attached I have used). In your case I would not OR them, but take the two outputs to separate transistors. You didn't say what pulse length the clock requires, but you may need to follow this with two monostables to lengthen the pulses. Then use these to drive an H-bridge. (QUOTE)

That looks very interesting . you have already used one I guess ! And successfully driven a bipolar transistor from the out put even though the diode gates drop a further .6v..I will look again at the outputs I've got but there did seem to be no more than ± 0.6v from the mean, which isn't surprising I thought when the supply voltlage is only 1.5 V.

The H bridge is a circuit idea I hadn't heard of until googling on motor drives a few days ago.

 

Yes, I've used those circuits successfully. The BAT85 diodes are Schottky, so drop less than 0.6V. I think the outputs of those clocks are H-bridges, since the coils are connected between them. But if you are going to use the two out-of-phase outputs separately, you don't need the diodes.

Ken

 

And maybe I don't need that 100 ohm load..I will investigate...

 

If I've understood your requirements correctly, something like this should do the trick:-

 

I will return shortly with more...

 

Would a simpler and rougher circuit be acceptable?

If you use a push-pull squarewave driver at 0.5Hz, (like a 555 timer) then the / edge and \ edge occur at 1 second intervals.

Then you just need to capacitor couple the clock coil (cap in series) so that each / and \ edge makes an energy pulse in different directions through the clock coil. The size of the cap roughly sets the energy in each clock pulse.

 

Would a simpler and rougher circuit be acceptable?

If you use a push-pull squarewave driver at 0.5Hz, (like a 555 timer) then the / edge and \ edge occur at 1 second intervals.

Then you just need to capacitor couple the clock coil (cap in series) so that each / and \ edge makes an energy pulse in different directions through the clock coil. The size of the cap roughly sets the energy in each clock pulse.

Thanks for the idea..Although I assume you mean that the 555 be triggered by the xtal osc pulses in some way . free running, the timekeeping would be pants.

 

If I've understood your requirements correctly, something like this should do the trick:-

I said earlier that H bridge was new to me..So I've spent some time considering it and think I can see how it works. And the 555 are allowing the output pulse width to be set. I note that you shown 250 ms in the simulation which may be longer that i necessary. The original pulses were too short I think.

When I did run the xtal osc module without the 100ohm load resistor I did get a +ve going pulse (wrt battery neg) from each output pad - as kMoffet had stated earlier. That really puzzled me ...until I took the time to look at the working of the h bridge. The little xtal osc module must have an H bridge in it.

And Alec...if you took the trouble to draw up and simulate that circuit especially for my query...extra thanks...When it's built I retrieve the thread and report back.

 

Following RB's suggestion to drive the slave via a cap, here's a simpler circuit.
C2 determines the slave pulse width, so can have a lower value if you want shorter pulses. Q2 and Q3 buffer the output of the 555, which otherwise would be working beyond its limit to give 220mA pulses.
R4 may need adjusting if you want equal 'tick' and 'tock' times. Unadjusted, the pulse interval could be, say, 1.1s,0.9s,1.1s,0.9s ......

 

Thanks for the idea..Although I assume you mean that the 555 be triggered by the xtal osc pulses in some way . free running, the timekeeping would be pants.

Yep sorry for that I should have explained more clearly.

My comment was mainly related to Alec_T's circuit using 555 timers, and a possible way to simplify it with a rough solution.

(and thanks to Alec_T who saw what I was rambling on about).

 

Ok..I really like the simplicity of the 555 circuit.

Am I right in thinking, that according to the simulation with the R values given, the npn transistor's output is biased mid rail and the 555 is alternately clocked on/off ? If so, that's novel - but is the biasing stable enough ?

Close to 50.50 duty cycle is near enough. Practical experimentation has stalled at the moment since one of the output slider pads has broken off. I need to get another clock unit. I'll secure the wires with hot melt next time.

Since I started on this further searches turned this : up http://sound.westhost.com/clocks/motors.html As has happened many times before Rod Elliot has already been there ! See fig 20 in particular..

And his "Clocks Menu" has lots of other relevant stuff I haven't had time to read yet.

 

Am I right in thinking, that according to the simulation with the R values given, the npn transistor's output is biased mid rail and the 555 is alternately clocked on/off ? If so, that's novel - but is the biasing stable enough ?

The master clock input is assumed to switch alternately between 0.1V and 1.3V with an 'average' DC level of 0.7V. R1/R2 form a voltage divider, so the Q1 'average' base voltage is 0.49V. This means Q1 is normally off and only the positive-going spikes of the master clock waveform are enough to turn Q1 on. Thus Q1 collector goes low, triggering the 555, every 2 secs. The 555 has a 1 sec period, so its output goes high and low alternately each second, causing C2 to charge and discharge alternately.

 

Of course ! I didn't twig that. Should have though because of the duty cycle question.