1 half adder and 2 half adder in adder/subtractor

Discussion in 'Homework Help' started by MicroMina, Jul 1, 2011.

  1. MicroMina

    Thread Starter New Member

    Jul 1, 2011
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    Hello all

    I'm having the following question:

    Design a digital circuit and implement it using 1 half adder and 2 full adders ONLY.
    The circuit has 3 bits as input (X) and 3 bits as output (Y).

    Y=X+1 (if x<=3)
    Y=X-1 (if x>3)

    I already designed a truth table and got the simplified functions of Y1,Y2,Y3
    where
    Y1= X1X2 + X1X3 + X2X3 = XY + Z(X xor Y)
    Y2= X xor Y xor Z
    Y3= X3'

    I spent hours trying to come up with a design that only has 1 half adder and 2 full adders and failed..
    Any idea how i can do this?

    Thank you.
     
  2. staticd

    New Member

    Sep 7, 2010
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    You should probably back up a little.

    A half adder does not have a Cin. A full adder does.

    Use the half adder for Y0 and and the full adder for Y1 and Y2.
     
  3. Georacer

    Moderator

    Nov 25, 2009
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    I don't quite get what staticd suggests. I hope he elaborates.

    Do you have any limits for the length of X and Y, as well as the length in bits of the half and the full adder?
     
  4. MicroMina

    Thread Starter New Member

    Jul 1, 2011
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    Thank you both for your reply

    I didn't get what staticd is trying to say either..
    what do you mean by the half adder does not have a Cin?

    @Georacer
    X and Y are 3 bits and I don't have any limits on the half and full adders.
     
  5. Georacer

    Moderator

    Nov 25, 2009
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    Since you know you that you have a 3-bit long X, what is the bit that will tell you if X is larger than 3 or not?

    Now that you have that information in 1 bit, let's examine your addition circuit. In the first case you want to add 1, in the second you want to subtract 1. Do you know about 2's complement? If so, you can subtract 1 through the addition of -1. Thus you only need an addition 3-bit circuit, with X in the one addendum and a variable number in the other (+1 or -1).

    The selection will be made, and the formation of the other addendum actually, by the information bit that I mentioned in the first paragraph.

    Is that clear?
     
  6. MicroMina

    Thread Starter New Member

    Jul 1, 2011
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    Thank you Georacer for your reply.
    I already handed out the assignment and what I did was take X1, X2, X3 (3 bits of X) as input to a full adder and the output of the full adder was Y1 and Y2.
    And I noticed from the truth table that Y3 = X3' so I need an inverter but I only have left 1 full adder and 1 half adder, so what I did was take X3 and 1 as inputs to a half adder and the output was Y3 and the other output I don't need.

    Well, I didn't exactly do what's required but I guess using fewer adders is practically better anyway.

    I understand what you said but I'm not quite sure how to implement it.

    The most significant bit of X (X1) will be the one determining wheather we are adding or subtracting 1.
    Now, what I have in mind is this, if X1 is 0 then I need to add one to X1,X2,X3 and if X1 is 1 then I need to subtract one from X1,X2,X3
    now I can use one full adder with X1,X2,X2 as inputs and two outputs, but i'm not sure what to do next.
     
  7. Georacer

    Moderator

    Nov 25, 2009
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    In the first case you need to add +1. To do so, you must add with a full adder 'X1''X2''X3' and '0''0''1'.

    In the second case you need to add -1. To do so, you must add the 2's complement of 1, which is '1''1''1'. The resulting addition is 'X1''X2''X3' and '1''1''1'.

    Looking at those two cases we can say that the addition we want to do in both cases is 'X1''X2''X3' and 'X1''X1''1'.

    Check it out with a few cases.

    Is that clear?
     
  8. MicroMina

    Thread Starter New Member

    Jul 1, 2011
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    this was really clear but this setup will only need 2 full adders, correct?
    (one full adder that adds X1,X2,X3 to get Y1,Y2 and another full adder that adds X1,X1,1 to get Y3)

    and one more question if you'd bare with me..
    What should be my approach when trying to solve one of those problems? I understand how the adders work and such but I sometimes feel confused when I try to implement them in a design. What is the correct procedure of thinking?

    Thanks so much for your help.
     
  9. Georacer

    Moderator

    Nov 25, 2009
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    You actually need only one 3-bit full adder. That is 3 1-bit full adders. Alternatively, you can use a 1-bit half adder for the LSB and two 1-bit full adders for the other two bits.

    Be careful! You don't want to add the digits of X. You want to add X+1 or X-1. That is pairs of X1,X1, X2,X1 and X3,1.

    Unfortunately, there isn't any standardized way to solve logic problems. Even Finite State Machine design requires you to build the mathematical model of the FSM in paper before converting it into a circuit.
     
  10. MicroMina

    Thread Starter New Member

    Jul 1, 2011
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    I got it this time and I cant thank you enough Georacer!
    Have a good day sir.
     
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