0-5 Counter...Urgent Help!!!!

Discussion in 'Homework Help' started by kjs_123, Nov 21, 2008.

  1. kjs_123

    Thread Starter Member

    Oct 16, 2008
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    Right, I designed a 0-5 Counter as shown below which counts 0-5 perfectly
    http://img92.imageshack.us/img92/834/05yl0.jpg

    Now I am kinda stuck on two things:
    1. I have to set the D input to High to count from 0-5(although it is counting 0-5) and when low do the reverse.
    2. add an extra input which when set high should hold its value and when set low should count normally.......

    *By adding a NOT gate to RESET the counter counts.....but whereas if the RESET is low then it doesn't count*

    I know the above is a basic digital design query....but as I am a beginner please help me out.....

    Thanks for looking
    KJ
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
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    If you designed it, you must know how it operates, and so knowing which D input to set should be a snap. Likewise a hold/count gate.
     
  3. kjs_123

    Thread Starter Member

    Oct 16, 2008
    22
    0
    Yeah i know how it works as I drew a state diagram and all.....
    But in the second part where it says "add an extra input which when set high should hold its value and when set low should count normally"

    Where should i put the extra input?:confused:
     
  4. beenthere

    Retired Moderator

    Apr 20, 2004
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    Think of a gate that will disable the clock pulses.
     
  5. kjs_123

    Thread Starter Member

    Oct 16, 2008
    22
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    What about OR/NOR the input..
     
  6. beenthere

    Retired Moderator

    Apr 20, 2004
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    That is a kind of gate that will pass/block the clock.
     
  7. kjs_123

    Thread Starter Member

    Oct 16, 2008
    22
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    Do beg your pardon....!!!

    It should be an NAND/NOR gate, which are frequently used as enable gates!!!:cool:
     
  8. beenthere

    Retired Moderator

    Apr 20, 2004
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    You can jam either type high or low - in any case it will stop the clock pulse.
     
  9. kjs_123

    Thread Starter Member

    Oct 16, 2008
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    Thanks for that beenthere .....but where will this extra input go....will it be at at D of DFF's????
     
  10. beenthere

    Retired Moderator

    Apr 20, 2004
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    It has to stop the clock into all flip flops. Moreover, it has to freeze the logic level at the correct state. Those flip flips clock on the transition, but it is not evident if it high to low or the converse. What you do not wish to happen is a clock transition at the time you apply the signal to block the clock.
     
  11. kjs_123

    Thread Starter Member

    Oct 16, 2008
    22
    0
    beenthere....I was just testing few things on my original digital design and noticed that If I put the RESET at high the clock did count from 0-5 but if the RESET was left at low then the clock did not count.....so is that answering my question below:confused:
     
  12. beenthere

    Retired Moderator

    Apr 20, 2004
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    If it's a D flip flop, the stae of the D input is transfered to the output when the clock pulse id applied. The SET and RESET inputs always override the clock and D inputs.

    You might benefit from obtaining the data sheet and reading how a 7474 flip flop works.
     
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