Synthesizable delay in Verilog

Thread Starter

Shagas

Joined May 13, 2013
804
Hello

Can someone advise how to implement delays in Verilog?
I've tried googling it and it either takes me to test benches or to some advanced papers which I don't understand.

Do I have to implement some sort of "request -> counter -> permission" sort of thing to get a proper delay?
 

JWHassler

Joined Sep 25, 2013
306
It's a little more complicated than it looks.
Here's a state-machine that steps through its sequence with each step taking a different number of clocks.

Rich (BB code):
//-----------------------------------------
// delay state machine

module State_Machine(
    input    clk,            
    input        [1:0]    In_Condition,
    output    reg    [1:0]    Out_Condition

    );
localparam    
IDLE    = 3'd0,    // 
ST_1    = 3'd1,    // 
ST_2    = 3'd2,    // 
ST_3    = 3'd3;    // 

// - - - - - - - - - - - - - - - - - - -
// a state-machine 
reg [3:0]state;    // state-reg
//- - - - - - - - - - - - - - - - - - - -
// a delay-clock for adjusting time of states
//   can be set to 1-7 clocks long
reg [2:0]ticker;// for time delays
wire TIMEOUT = (ticker == 3'h0);

always @(posedge clk) begin

    //------ delay-clock: if non-zero, it ticks down to zero ---------
    if (ticker != 3'd0)    ticker    <=    ticker - 3'b1;
    
    // state-machine
    case(state)
        IDLE:
            begin
                Out_Condition[1:0]    <=    '0;        // both go to zero in idle-state
                if (In_Condition[0] ) begin            //  when the first input goes high
                    ticker    <=    3'd2;                //   ...set delay to 2 clocks
                    Out_Condition[1:0]    <=    2'b01;    //   ... assert first output
                    state    <=    ST_1;                //   ... go to state ONE
                    end
                end    // of 'idle'

        ST_1:
            begin
                if (In_Condition[1]&& TIMEOUT) begin//  when the first input goes high AND MIN DELAY ELAPSES
                    ticker    <=    3'd3;                    //   ...set delay to 3 clocks
                    Out_Condition[1:0]    <=    2'b10;        //   ... assert second output
                    state    <=    ST_2;                    //   ... go to state TWO
                    end
            end    // of 'ST_1'
        ST_2:
            begin
                if ( TIMEOUT) begin                        // state two is ONLY a delay
                    Out_Condition[1:0]    <=    2'b11;        // ... at the end of which BOTH outputs are asserted
                    ticker    <=    3'd4;                    // ... another delay begins
                    state    <=    ST_3;                    // ... and we go to state THREE
                    end
                end    // of 'ST_2'
        ST_3:
            begin
                if ( TIMEOUT )                            // state three just delays, then goes to IDLE-state     
                state        <=    IDLE;
                end    // of 'ST_3'
    default: state    <=    IDLE; 
    endcase
end // always posedge clk
    
endmodule
 

kubeek

Joined Sep 20, 2005
5,794
Best approach is to imagine how you would do it with real circuits, and then convert to verilog.
So my approach would be an n-bit counter, with clock and reset inputs and an output.
on each clock:
When reset is low, increment the counter, then compare it with the timeout value. If you reach the timeout, set the output.
When reset is high, set count to 0 and reset the output.
Use the output to enable the execution of whatever you wanted to delay. You should be able to synthesize gated clocks for example.
 

Thread Starter

Shagas

Joined May 13, 2013
804
Hmm yes I was planning to do it similarly , just wanted to check if there was some other way of doing it.
 

Brownout

Joined Jan 10, 2012
2,390
You can chain some logic together and use their combined propagation delays. Since all modern design is synchronous these days, there is really no reason to do this.
 
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