This diagram is given as ladder logic for full adder in the section Volume IV - Digital » COMBINATIONAL LOGIC FUNCTIONS » Full Adder.
The last rung should be C1 and C2 in parallel to form an OR gate instead of series connection given.
Thanks manulal for pointing us to this error.
This diagram is given as ladder logic for full adder in the section Volume IV - Digital » COMBINATIONAL LOGIC FUNCTIONS » Full Adder.
The last rung should be C1 and C2 in parallel to form an OR gate instead of series connection given.
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