This page: http://www.allaboutcircuits.com/vol_4/chpt_10/5.html
The following comes out of the blue:
This would manifest as a real effect if the set/reset were being controlled by a push-button. The push button might be held down for large amounts of time, causing the flip-flop to settle on some unexpected value for long enough for something unexpected to happen.
My feedback would be to introduce and explain the invalid state with more words. Of course, this is from a novice...
The following comes out of the blue:
I assume the invalid state is that Q and Q' are both 0. Only when writing this did I realize that this isn't the entire problem. When the clock pulse goes low, we can't say for sure what the next state of the flip-flop will be and thus the flip-flop goes insane.It is important to note that the invalid state for the S-R flip-flop...
This would manifest as a real effect if the set/reset were being controlled by a push-button. The push button might be held down for large amounts of time, causing the flip-flop to settle on some unexpected value for long enough for something unexpected to happen.
My feedback would be to introduce and explain the invalid state with more words. Of course, this is from a novice...
The S-R flip-flop has two flaws that must be dealt with. The first is the illogical result of Q and Q' having the same value when R and S are both 1. This happens only in the instant the clock enables the circuit. Thus if your circuit depends upon Q being the same as not-Q', you might see inexplicable behavior. Second and worse, this type of flip-flop has an inherent race condition that manifests when in this state and the clock disables the circuit. The values of Q and Q' will become logical but undependable. That is, Q could be 1 for one flip-flop but 0 for another flip-flop. In a cruel world, it would be possible for the same flip-flop to exhibit different behavior from day-to-day. This inconsistency is caused by real-world imperfections in the silicon and wiring. The NOR gate with the fastest silicon (or shortest connecting traces...) is going to produce a 1 first, and this will cause the other NOR gate to produce a 0.
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