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  #1  
Old 02-05-2012, 03:05 PM
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Default Divide by 2 flipflop with 3 NAND gates?

Hi, I need a divide by 2 "flip flop" logic device, and rather than add an entire new flip flop IC to the design I have 3 spare NAND gates.

Does anyone know if it is possible to make a divide by 2 type flip flop using just the 3 NAND gates?

The input is a logic level 0v-5v square wave with a duty of 40-60%, somewhere around 10kHz and I need an output at half the frequency and 50% duty cycle. It doesn't matter if it triggers from the / edge or the \ edge of the input signal, as long as it divides by 2 and gets exactly 50% duty.

I have made S/R flip flops from NAND gates, which just takes 2 gates, so maybe it's possible to add another NAND gate and make it a toggle type (divide by 2) flip flop? I've been working with PICs for so many years that I'm rusty on the fine details of working with discrete logic gates, I think the last time I tried to make something complex out of gates was in the late 70's.

Thank you.
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Old 02-05-2012, 03:26 PM
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Any other logic at all? I cut my teeth on Master/Slave FF, it might be possible to do something with diode steering.
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Old 02-05-2012, 03:26 PM
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I believe you would need more gates. Here's a reference discussing the various types of FFs.
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Old 02-05-2012, 04:18 PM
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Can any other components be used too? Like capacitor, resistor, diode?
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Old 02-05-2012, 04:19 PM
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That is what I was asking in post #2.
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Old 02-05-2012, 08:55 PM
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You would need six NAND gates, and one of them would need to have three inputs.

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Old 02-05-2012, 10:06 PM
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I think it's possible with using just 3 NAND gates, Take a look to the link given on the post #3, From there on the diagram of the D- flip-flop we can Conclude this equation:

C= Clock
D= Data
Q= Output

Q(t+1) = ((DC)' + (Q + (D'C)' )' )'

After Simplification:


Q(t+1) = ((DCQ)' . ( DC (D + C') )' )'

Q(t+1) = ((DCQ)' . (DC)' )'

So I think it's possible With just 3 NAND, one of them would need to have three inputs.

Maybe I'm wrong!
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Old 02-06-2012, 06:21 AM
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To divide by two you need an edge-triggered FF and that requires more than three gates.
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Old 02-06-2012, 12:05 PM
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Quote:
Originally Posted by holnis View Post
I think it's possible with using just 3 NAND gates, Take a look to the link given on the post #3, From there on the diagram of the D- flip-flop <snip>
Unfortunately, that D-type FF schematic in that link isn't correct. If Q\ is connected to D, and then CP goes high, the circuit will oscillate at high frequency.

As crutschow mentioned, it needs to be edge-triggered, and that takes more gates.
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Old 02-06-2012, 03:50 PM
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Thank you Crutschow for the great link on flip-flops! Ok so I don't feel so bad now that my couple of quick attempts to make a /2 circuit out of 3 NAND gates didn't work.

The circuit has three 2-input NAND gates spare. They are schmidt trigger input type. The other NAND gate is used as an oscillator, and the desired result from the one chip is to get a rough frequency output but at exactly 50% duty (hence the /2 idea).

I don't want to add other chips but maybe it can be done with a couple of extra discretes? Since the oscillator is a fixed freq (say +/-10% freq accuracy) it might be possible to use an RC timed circuit on the output to cause the /2 toggling?

I also considered using a dual flipflop IC with one FF being the oscillator and the other FF as the /2, but I could not find an easy source for a FF with a schmidt trigger input as the oscillator needs to be fairly reliable so a schmidt input is desired.

If it starts getting too parts-heavy I can always use a $1 PIC, but I prefer if possible to use a 15 cent quad NAND gate. Any suggestions appreciated.
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