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  #1  
Old 05-18-2011, 06:33 AM
BruceBruce BruceBruce is offline
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Default 4 bit up/down counter project using D flip flops

I'm trying to design and test a 4-bit version of an Up/Down Counter using D Flip flops. I need it to be Up'/Down = 0 then the circuit should behave as an up counter. If Up'/Down = 1 then the circuit should behave as a down counter. I also need to create an input waveform file to test the procedure in a "full count" up and down.

Oh i need to design this in Quartus II software. It can be a schematic or VHDL code.

Thanks for the help hopefully.
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Old 05-18-2011, 02:22 PM
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Oh, aren't you in luck. Take a look here, lower half of the page:
http://www.allaboutcircuits.com/vol_4/chpt_11/3.html

Come back with your questions.
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Old 05-19-2011, 02:14 AM
BruceBruce BruceBruce is offline
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Thats an up/down counter using a jk flips flops. i need it with d flip flops. I can write the code for a Four bit counter with d flip flops but i dont know how to make it an up and down counter.
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Old 05-19-2011, 06:31 AM
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would i design it similarly to that with the d flip flops instead of the jk flip flops and have the OR gates going into the D input instead of the J and K inputs. How would the first D input go? (pictures help lol im good with those)
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Old 05-20-2011, 04:30 AM
BruceBruce BruceBruce is offline
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this is what i got so far:


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well i dont know what to plug into the d input of the first FLip flop. In the diagram for the JK flip flop 4 bit counter it had Vdd as the first input to j and k. What is Vdd and how do i incorporate that into my diagram. Also the "up/down" is that just a regular input labeled up/down? i know the q0-q3 are all the outputs but where do i end that last "NOT Q" to?

Hopefully you guys can answer this and help me fix the drawing. I got tell friday at midnight to turn it in for a grade. Ill owe whoever helps me out big time. If you would like to email me than please send it to <SNIP>. Thank you.

Last edited by bertus; 05-20-2011 at 04:55 AM. Reason: removed email address to protect you from spam
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Old 05-20-2011, 05:28 PM
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I haven't been on a computer in the last 48 hours, hence the late reply.

Let's think about the difference between a JK FF and a D FF and how we can convert the second into the first, to serve our purpose.

In the schematic I posted you, you will notice that a signal coming from an OR gate drives both J and K inputs of a JK FF, flipping its state each time it has a value of '1'. The D FF doesn't have that functionality inherently. We must build some circuitry to produce it.
Remember: On the presence of a '1', we want the FF to switch state. What if we take the Q' output of the FF and AND it through a gate along with the '1' signal? Do you see how that would work?

You can find another proposition in this thread:
http://forum.allaboutcircuits.com/sh...ad.php?t=45624
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Old 05-20-2011, 08:23 PM
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Also in the quartus program how do i get "Q NOT"? there isnt a pin for it on the D Flip Flop icon. do i just run a Not gate off the Q? i attached a pic of it
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Old 05-20-2011, 08:28 PM
BruceBruce BruceBruce is offline
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heres the new design. let me know what you think. I gotta turn this in by midnight tonight(california time PST) GeoRacer.
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Old 05-20-2011, 10:58 PM
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That not quite right. Since you seem to not handle a new schematic well, why don't you take the AAC schematic as it is and replace the JK FF, with a module that will be comprised of a D FF, and an AND gate.

You have the J/K common input of you module which should switch state when the signal from the OR gate on the schematic is '1'.
In other words, you need to find a way to give the D FF input a Q when the OR output is '0', and Q' when the OR output is '1'.
That can be accomplished with a 2-to-1 MUX.

Can you figure out how?

The first FF will have its hypothetical OR input raised to '1' permanently (or just connected to its Q' for economy).
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Old 05-20-2011, 11:33 PM
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What are these? I haven't run into those logic symbols before,

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