I am trying to troubleshoot a system with registers that supposed to go parallel in - series out and then series-in parallel-out. I believe that I have the concept right with D-latches, using clock and enable gates to load and unload each latch in sequence but when I run it on multisim my parallel outputs do not correspond to the inputs in any way. I have not been able to figure out what the problem is. Am I misundeerstanding something? Any input is welcome.
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