Hi,
Im currently brain storming for a project that will use two 7495s (4-bit parallel-in serial-out) to perform serial communication. The first one will take parallel-in, serial-out the second one will take that serial-in, and display parallel-out. For reference of the chip, visit
http://www.ee.washington.edu/stores/DataSheets/74ls/74ls95.pdf
Being new to all this stuff, I am very unsure how to do this project, but Ive come up with a couple or ideas and questions regarding this project, please feel free to correct any misconceptions and fill in the blanks cause I sure could use the help.
Question 1:
Is there some trick to converting parallel input to serial output, and vice versa? Or am I correct in the following observations?
Register # 1 (parallel-in: serial-out)
The first thing that comes to mind is that S (the mode) would have to be 1 to take in the parallel input but the output will also read parallel. I could switch S to 0 to shift the bits out, however the bits will be read backwards.
Question 2:
Should I shift left to get the correct result? According to my notes, in order to shift left, I have to rewire Q3 to P2, Q2 to P1, and Q1 to P0.
Question 3:
It also states you should be in parallel mode to shift left wouldnt this interfere with the original parallel input?
Register # 2 (serial-in: parallel-out)
In this register the mode S will be 0 (serial-in), and the input will come from Q0 (if bits are shifted left).
Question 4:
Once all 4-bits are in their appropriate places, do I just set S to 1 to read the parallel output?
Question 5:
There are two clocks to each 4-bit register, why are two clocks needed? I know there is one assigned to each mode, but I dont understand why they would need different signals.
I DO know there is an inversion needed between the clock cycles for register 1 and register 2. But what relationship should the clock signals (within the same register) have?
Im currently brain storming for a project that will use two 7495s (4-bit parallel-in serial-out) to perform serial communication. The first one will take parallel-in, serial-out the second one will take that serial-in, and display parallel-out. For reference of the chip, visit
http://www.ee.washington.edu/stores/DataSheets/74ls/74ls95.pdf
Being new to all this stuff, I am very unsure how to do this project, but Ive come up with a couple or ideas and questions regarding this project, please feel free to correct any misconceptions and fill in the blanks cause I sure could use the help.
Question 1:
Is there some trick to converting parallel input to serial output, and vice versa? Or am I correct in the following observations?
Register # 1 (parallel-in: serial-out)
The first thing that comes to mind is that S (the mode) would have to be 1 to take in the parallel input but the output will also read parallel. I could switch S to 0 to shift the bits out, however the bits will be read backwards.
Question 2:
Should I shift left to get the correct result? According to my notes, in order to shift left, I have to rewire Q3 to P2, Q2 to P1, and Q1 to P0.
Question 3:
It also states you should be in parallel mode to shift left wouldnt this interfere with the original parallel input?
Register # 2 (serial-in: parallel-out)
In this register the mode S will be 0 (serial-in), and the input will come from Q0 (if bits are shifted left).
Question 4:
Once all 4-bits are in their appropriate places, do I just set S to 1 to read the parallel output?
Question 5:
There are two clocks to each 4-bit register, why are two clocks needed? I know there is one assigned to each mode, but I dont understand why they would need different signals.
I DO know there is an inversion needed between the clock cycles for register 1 and register 2. But what relationship should the clock signals (within the same register) have?