Question: Show how an SR flip - flop can be constructed using a D flip-flop and other logic gates.
Okay so the first thing I do is ask myself how an SR flip flop works. (Let's assume we're using a NOR SR FF)
Okay so if S = R = 0 then it will hold its state.(I.e. Q(t+1) = Q(t) )
If S = 0 and R = 1 then Q(t+1) = 0.
If S = 1 and R = 0 then Q(t+1) = 1.
If S = R = 1 then it's invalid.
Now I ask myself how does a D flip-flop works.
Well we know that a the output Q(t+1) is going to follow D only on the positive edge of the clock.
So the only time we care about is when our clock has a positive edge.
Now if our clock has a positive edge and D = 1 then Q(t+1) = 1.
Similarly, if our clock has a positive edge and D = 0 then Q(t+1) = 0.
If our clock doesn't have positive edge and D = 0/1 then Q(t+1) = Q(t).
Now back to the original question, I have to construct an SR flip-flop using D flip-flops and other logic gates. How do I work my way towards the solution?
I thought I had decent understanding of how SR and D flip-flops work but I don't know how to work my way towards a solution in a situation like this.
Thinking about the differences between and SR FF and D FF:
- An SR FF doesn't depend on any sort of clock, so somehow using D flip-flops and logic, I have to "eliminate" the clock in such a way that when values for S and R are applied, the clock will have a positive edge.
- An SR FF (If we think about the SR NOR FF) is invalid for S = R = 1, so somehow I have to incorporate an "invalid state" using D flip-flops.
- An SR FF will hold its state when S = R = 0, while the D flip flop will hold its state while the clock is low (or on a negative edge). If I can guarentee that the when S = R = 0 that the clock is low(or on a negative edge) I should be able to manage the case S = R = 0.
I can't get any solid progress down on actually designing this thing. Am I attacking the problem in the wrong way? What should I be thinking about and what should I be asking myself?
Thanks again.
Okay so the first thing I do is ask myself how an SR flip flop works. (Let's assume we're using a NOR SR FF)
Okay so if S = R = 0 then it will hold its state.(I.e. Q(t+1) = Q(t) )
If S = 0 and R = 1 then Q(t+1) = 0.
If S = 1 and R = 0 then Q(t+1) = 1.
If S = R = 1 then it's invalid.
Now I ask myself how does a D flip-flop works.
Well we know that a the output Q(t+1) is going to follow D only on the positive edge of the clock.
So the only time we care about is when our clock has a positive edge.
Now if our clock has a positive edge and D = 1 then Q(t+1) = 1.
Similarly, if our clock has a positive edge and D = 0 then Q(t+1) = 0.
If our clock doesn't have positive edge and D = 0/1 then Q(t+1) = Q(t).
Now back to the original question, I have to construct an SR flip-flop using D flip-flops and other logic gates. How do I work my way towards the solution?
I thought I had decent understanding of how SR and D flip-flops work but I don't know how to work my way towards a solution in a situation like this.
Thinking about the differences between and SR FF and D FF:
- An SR FF doesn't depend on any sort of clock, so somehow using D flip-flops and logic, I have to "eliminate" the clock in such a way that when values for S and R are applied, the clock will have a positive edge.
- An SR FF (If we think about the SR NOR FF) is invalid for S = R = 1, so somehow I have to incorporate an "invalid state" using D flip-flops.
- An SR FF will hold its state when S = R = 0, while the D flip flop will hold its state while the clock is low (or on a negative edge). If I can guarentee that the when S = R = 0 that the clock is low(or on a negative edge) I should be able to manage the case S = R = 0.
I can't get any solid progress down on actually designing this thing. Am I attacking the problem in the wrong way? What should I be thinking about and what should I be asking myself?
Thanks again.