Voltage spikes at grounded logic inputs

Hey everyone!

I'm an undergraduate in a physics lab, and I have been charged with making a fail-safe system for one of the experiments. I'm having some troubles, and wondered if you guys could help out.
As part of my system I have built a circuit (schematic attached) that when it receives a signal it shuts off another part of the experiment. I am monitoring 6 different parts of the experiment, and I have split those parts into two sections on the circuit. One section receives signals from 3 flow switches, and the other receives signals from a flow switch and the comparator. When the flow switch or comparator leaves the defined range my circuit should send a signal to shut off different parts of the experiment and not allow them to turn on. This is done by recieveing a signal through an OR gate, and sending the output of the OR gate to an RS flip-flop. The flip-flop is then connected to some relays that control different parts of the experiment. The circuit that I have built functions how I want it to. However it seems to have be very sensitive to ESD and transient changes in the ground. That is, whenever there is an ESD near or on the box containing it the flip-flop gets triggered and changes state. Also, when an electronic device is plugged into a receptacle in the wall (near to where my power supply is plugged in) the flip-flop gets triggered and changes state. I think this is due to a voltage spike at the input at the OR gate (which are all grounded when not receiving a signal).

A few notes:
1. I've made sure that everything is grounded through the ground coming through my power supply, including all of the unused inputs to the OR Gate.

2. I've checked one of the inputs at one of the OR gates with an oscilloscope, and there is a very transient voltage increase (or decrease) when I plug or on unplug something into a receptacle (****The device must be on before being plugged in to consistently repeat this phenomena. This is probably not good practice, but I need to make my circuit so that it isn't sensitive to this*****). I think this may be the cause of my problems. However, I don't know how to fix this issue.

3. I've considered adding an inductor through my ground to try to suppress the voltage spikes. However, I think I would need a very large inductor, which would be impractical (maybe).


4. A friend suggested I look into using an opt-isolator. I've done some reading on this, but I'm not sure where I would implement it.


I'm VERY new to electronics and am probably violating a ton of rules. With that said, I would love constructive criticism on the circuit and some suggested solutions to my issue.


Thanks in advance!
Thenobsta

Have you wired 100n ceramic caps close to each IC.
This will help in stabilizing the supply during gate out put switching periods thus improving transient responses

Hello Thenobsta,

Lots of info there. Good that you attached a schematic.

This might seem a bit particular at first, but the convention for schematics is to have the inputs coming from the left, and the outputs flowing towards the right; the more positive voltages towards the top of the schematic, and the more negative towards the bottom. If you try to follow that convention as much as possible, your schematics will be much easier to comprehend. Having most of your components sideways, with inputs from the top and flowing out the bottom is a bit unusual, and makes it harder to read/comprehend.

Some of us on the forums are "senior" in more ways than just post counts. My eyes aren't what they once were. It would be most helpful if you could export your schematic to a graphic with higher resolutioon; say 120dpi to 150dpi. .png format is preferred, as it is not "lossy" like .jpg/jpeg format images. If it is difficult to read, one may make mistakes in interpreting it, or simply bypass your post in search for something more easy to read.

It looks like you are using an LM340 regulator, I can't tell if it's a -05 or -06. You do not show capacitors on either the input nor output.

You should have a 0.22uF or 0.33uF cap across the IN and GND pins, immediately adjacent to the regulator to help prevent instability/oscillations. Although some manufacturers claim that an output cap is not necessary, you should include a 0.1uF ceramic or metal poly cap immediately adjacent to the output. I have observed 78xx/340xx regulators oscillate at frequencies in the MHz range if the caps are omitted. The expense is minor compared to the potential for trouble.

Every IC must have a 0.1uF capacitor across it's supply pins. If you omit them, you are begging for trouble.

It looks like you are using transistors as emitter followers rather than saturated switches. This will result in a voltage drop of around 0.7v from base to emitter, and higher power dissipation in the transistors. You should be using them as saturated switches instead.

To use an NPN transistor as a saturated switch:
1) The emitter is connected to ground.
2) The collector sinks current from the load
3) Current through the base switches the current sink on and off.
The base requires a current limiting resistor (Rb). Base current should be 1/10 the desired collector current (Ic).

Example:



If you are driving from TTL or CMOS levels, you must also take into consideration the current limits/voltage drops from the TTL/CMOS inputs.

By the same token, you need to properly calculate current limiting resistors (Rlimit) for your LEDs.

The generic formula for LED Rlimit is:
Rlimit >= (Vsupply - Vf_LED(typ))/Desired_Current
where:
Vsupply = the difference between your voltage supply "rail" and your current sink point; usually ground.
Vf_LED(typ) - the datasheet specification for the typical forward voltage at a given current.
Desired_Current - your desired LED current. For longest life, stay under the typical current.

Example: you have a red LED, 2.3V typ @ 20mA, your supply is 5v, to ground.
Rlimit >= (5v-2.3v)/20mA
Rlimit >= 2.7/0.02
Rlimit >= 135 Ohms.
A table of standard resistance values is here:
http://www.logwell.com/tech/components/resistor_values.html
Bookmark that page.
Refer to the green columns, as E24 values are commonly available. You can get E48 and higher, but you pay a premium price.

Scanning down the columns, you will see that 135 is not a standard E24 value. If you do not care about reliability, you might choose a 130 Ohm resistor. However, 150 Ohms would be a more safe choice.

So, time to recalculate what the new current will be.
I=E/R, or Current in Amperes = Voltage/Resistance
I=(5-2.3)/150
I=2.7/150
I=0.018A = 18mA

Then you need to calculate the power rating requirement for the resistor.
P=EI, or Power in Watts = Voltage * Current in Amperes
E=(5-2.3)*18mA = 2.7*.018 = 0.0486 Watts = 46.8mW.
We double that for reliability's sake, so 97.2mW. You can use a resistor rated for 1/10W or higher.

Don't forget to do the same thing for your base current limiting resistors.

Another thing to consider, if the connections to the circuit you show come from external devices, is that CMOS inputs are ultra-sensitive to static discharges and the input voltage exceeding the chip supply.

Either can destroy the IC or cause erratic operation.

Every externally fed input should have a pullup or pulldown resistor to prevent it floating, plus a series resistor between that and the actual IC input pin to limit the current if the external voltage exceeds the supply.

Both the pullups and series resistors can be quite high value, 10K or 100K whatever is convenient.

Also, make sure you have flywheel diodes across the relay coils, otherwise they will produce a high voltage spike on switchoff.

Adding to what Robert mentioned about ESD considerations, you should use diodes to clamp the inputs so that they cannot go much below ground or above Vcc.

Something like this:



Rin is 10k to limit current through clamping diodes D1 and D2, in case the IN voltage exceeds Vdd or GND.
Rpullup is 10x the value of Rin; it keeps the input from floating, but still allows the input to vary between about 1/11 Vdd to Vdd, which is an acceptable range for logic levels.

Rpulldn keeps the lower input at a ground potential. You can still pull the input high with a jumper to Vdd or a jumper to another portion of logic for testing if desired. However, if you hard-wire it to GND or Vdd, you lose that ability.

This doesn't relate to your problem, but 2N4416 is a small-signal N-channel JFET (you show an NPN), and will not work in your circuit.

Good call, Ron. The text is so small I had a heck of a time trying to read anything.

Thanks for all of the advice guys!!!

Thanks a ton for the comments on how to draw the circuit. I've been asking around for for some convention on this, but nobody seems to be able to help.

I think the transistor is a 2n4410 NPN transistor. Sorry about that. I'm still trying to figure out the program they use in the lab. I'll work on making the schematic a bit clearer too.

I will try to implement (and understand) these suggestions in my circuit and see if performance improves. It might be a while though. My schoolwork is pretty intense right now.
I'll probably post back this weekend with a report and some more questions.

Thanks again!
thenobsta