Creating CMOS inverter

Hi,

I want to build a CMOS inverter circuit (1 pmos on top, 1 nmos on bottom) on a breadboard. Is this possible to do with an nmos and a pmos you would buy from mouser or digikey? Or do you have to buy a special IC to use it? Can you find an NMOS and a PMOS that have the same parameters that would allow it to work? Further, I want a decent amount of current to flow through these, so could I make this inverter from typical power mosfets ?

What kind of voltage and current do you plan on working with?

Here is a quick sim of the idea. Note the "shoot-through" current (IDm2) as a function of Vdd. You would have to design a "stabilized bias" network similar to what is used in a class AB audio amplifier to control the quiescent current for supply voltages above ~4V.

5 volt pulsed input at the gates, and the inverter wouldn't be driving more than a 1 amp load.

surfline said:

5 volt pulsed input at the gates, and the inverter wouldn't be driving more than a 1 amp load.

Click to expand...

That still leaves you with a shoot-through current of 24A (purple trace) as the inverter swings through the center point...

Other than fabrication of the base MOSFET transistors, how does CMOS chips do it?

To the OP:

Give us better information as to the load. We can help you make drivers that won't have as much shoot through. It is a problem with any circuit that can go rail to rail.

With the right drivers you can even use two N-ch MOSFETs to do the same thing.

Bill_Marsden said:

Other than fabrication of the base MOSFET transistors, how does CMOS chips do it?
...

Click to expand...

Answer is: it is not possible to completely eliminate shoot-through. In CMOS processes, the Vth of the P and the N devices are carefully controlled, and are tailored to the nominal Vdd voltage for the process, and the W/L of the transistors are also chosen in part to reduce it. Every CMOS gate exhibits it to some extent. The total current of the chip is a function of how many gates are switching per unit time. The shoot-through is minimized by having internal nodes slew through the mid-point as fast as possible. Lower voltage processes ~1.5V minimize it because the sum of VthP and VthN can be greater than Vdd.

By shoot through, I'm assuming you're talking about the time when the NMOS and the PMOS are both on? That's why, my original question was asking are there any good NMOS & PMOS transistor combo's that have pretty identical Vt's.

Specifically, I'm trying to use the inverter as a driver from A PWM output from PIC micro controller (0-5V PWM, 25mA max output) which is going to drive 4 power mosfet's. The four power mosfets are turning on / off 30 amp load. I shouldn't need more than one amp from the driver to charge the four power mosfets gate capacitance's.

Mosfets have thousands of paralleled "cells". Each cell is a tiny Mosfet.
Cmos ICs are made of individual Mosfet Cells that have a low current. When boith the N-mos and P-mos transistors are turned on then the shoot through current is not high.

What about if you're not using an IC?

surfline said:

What about if you're not using an IC?

Click to expand...

Then you can use separate Mosfets that contain thousands of Mosfet cells so that they conduct 40A or more when they are both turned on.
A Cmos IC draws maybe 20mA when both Mosfets are turned on. A huge difference.