Carry save adder Verilog help

I've designed my CSA and it works in Active-HDL. The values are correct. However, I wanted to add testbench code to the project so that it can be verified in command-prompt situations. I get the Active-HDL error:

Error: VCP2605 CSA.v : (117, 1): Connection error at port So. Only l-value NET expression is allowed for OUTPUT/INOUT port.

This program calls on a ripple carry adder to do work for the carry save adder. Those parts work fine together and the resulting values are correct in Active-HDL. The problem is in the testbench code.

I know it is probably a Verilog fundamental concept, like I misrepresented the port or something. I'm just starting Verilog, and I don't know if this is a user error or a program error. If you have sharp eyes and can see the problem please let me know. I have marked the line that the Active-HDL compiler screams about below. Thanks.


//4-bit ripple carry adder
module RCA (A,B,Ci,So,Co);
//outputs
output [3:0] So ;
output Co ;
//inputs
input [3:0] A ;
input [3:0] B ;
input Ci ;
//internal wiring
wire c1,c2,c3,c4;
wire g0,g1,g2,g3;
wire p0,p1,p2,p3;
//g = A * B
assign g0=A[0]&B[0];
assign g1=A[1]&B[1];
assign g2=A[2]&B[2];
assign g3=A[3]&B[3];
//p = A + B
assign p0=A[0]|B[0];
assign p1=A[1]|B[1];
assign p2=A[2]|B[2];
assign p3=A[3]|B[3];
//c = g + (p * Ci)...
assign c1=g0|(p0&Ci);
assign c2=g1|(p1&g0)|(p1&p0&Ci);
assign c3=g2|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&Ci);
assign c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&Ci);
assign Co=c4;
//S = g XOR p XOR C
assign So[0]=g0^p0^Ci;
assign So[1]=g1^p1^c1;
assign So[2]=g2^p2^c2;
assign So[3]=g3^p3^c3;
endmodule


//8-bit carry save adder
module CSA(A,B,Ci,So,Co);
//outputs
output [7:0] So;
output Co;
//inputs
input [7:0] A,B;
input Ci;
//internal wiring
wire [3:0] stemp1,stemp0;
wire c4;
wire c80,c81;
//utilize RCA for CSA
RCA RCAin(A[3:0],B[3:0],Ci,So[3:0],c4);
RCA RCA1 (A[7:4],B[7:4],1'b1,stemp1,c81);
RCA RCA0 (A[7:4],B[7:4],1'b0,stemp0,c80);
//conditional assignments
assign So[7:4] = c4?stemp1:stemp0;
assign Co= c4?c81:c80;
endmodule


//testbench code

module tb_dec2_4;
reg [7:0] a,b,e,f;
wire [9:0] s;
reg [9:0] answer;
reg failed;
integer i;

// This is a testbench for an asynchronous non-pipelined 8-bit 4-value adder.
// this testbench assumes a module called "adder" that starts like this:
// module adder(a, b, e, f, s);
// input [7:0] a, b, e, f;
// output [9:0] s;



//error message comes from the next line:

//Error: VCP2605 CSA.v : (117, 1): Connection error at port So. Only l-value NET expression is allowed for
//OUTPUT/INOUT port.


--------->CSA uut(a,b,e,f,s);
initial begin
$write("simulation starting.\n");
a=0;b=0;e=0;f=0;
failed=0;
for (i=0; i<20; i=i+1) begin
a=$random;
b=$random;
e=$random;
f=$random;
#1;
answer=check(a,b,e,f);
$write("A %b B %b E %b F %b S %b answer=%b", a,b,e,f,s,answer);
if (s==answer) begin
$write(" CORRECT\n");
end
else begin
$write(" INCORRECT\n");
failed=1;
end
end
$write("simulation ending.\n");
if (failed) $write("some tests FAILED.\n");
else $write ("all tests succeeded.\n");
$finish;
end
function [9:0] check;
input [7:0] a,b,e,f;
reg [9:0] sum;
begin
sum=a+b+e+f;
check=sum;
end
endfunction
endmodule