We are asked to do the following (we are designing this circuit using the Logic Works program):
Connect two 8-bit shift registers to perform shift operations in the following steps:
1. Load shift register 1 with the parallel code 10110101.
2. Convert the parallel code in shift register 1 into a serial code with the MSB (most significant bit) going first, and transmit the serial code into shift register 2 until the latter receives the entire code in a reverse order, i.e., 10101101, while the code in shift register 1 is unchanged and maintained as 10110101. Hand in the circuit diagram and the waveforms of the clock and the serial code signals transmitted between the two registers.
A screenshot of the circuit I have designed thus far can be found here: http://img26.imageshack.us/img26/5859/shiftregisterscircuitdi.png
The inputs and clocks have the following parameters:
the clock for load for shift register 1 has a low-time of 10 and a high-time of 160 (the idea is that it is initially 0 to load the parallel code, and then once it is loaded, load should be 1 from that point on so that shift register 1 just continuously shifts the 8-bit number)
The clocks for both shift register 1 and shift register 2 have a low and high time of 5.
As can be seen on the circuit diagram, the output of Q7 (i.e., reg1 MSB signal line) is connected to SI for shift register 1 so that once something is shifted out it is then shifted back in to the LSB of shift register 1. The output of Q7 (reg1 MSB signal line) is also connected to SI for shift register 2 so that the 8-bit number can be received in the reverse order for shift register 2 (i.e., the first bit shifted out of shift register 1 goes to the LSB of shift register 2 and so on and so forth).
The waveform for the reg1 MSB signal line is correct, as when the parallel code is first loaded it has a value of 1, then after the first shift it has a value of 0 (and the 1 that was the MSB is shifted out and then goes to the LSB), and then after the second shift it has a value of 1, and so on and so forth, following the code sequence of 10110101, as it should. However, the waveform for the reg2 MSB signal line is not producing the correct result (i.e.,10101101), but I am not sure why this is the case. I felt like the way I designed the circuit is the logical (and correct) way to go about designing this circuit, so if there are any noticeable issues/problems with my design that would explain why I am getting incorrect results for the reg2 MSB signal line, I would certainly appreciate it if they could be brought to my attention, as I am fairly new to designing circuits.
Connect two 8-bit shift registers to perform shift operations in the following steps:
1. Load shift register 1 with the parallel code 10110101.
2. Convert the parallel code in shift register 1 into a serial code with the MSB (most significant bit) going first, and transmit the serial code into shift register 2 until the latter receives the entire code in a reverse order, i.e., 10101101, while the code in shift register 1 is unchanged and maintained as 10110101. Hand in the circuit diagram and the waveforms of the clock and the serial code signals transmitted between the two registers.
A screenshot of the circuit I have designed thus far can be found here: http://img26.imageshack.us/img26/5859/shiftregisterscircuitdi.png
The inputs and clocks have the following parameters:
the clock for load for shift register 1 has a low-time of 10 and a high-time of 160 (the idea is that it is initially 0 to load the parallel code, and then once it is loaded, load should be 1 from that point on so that shift register 1 just continuously shifts the 8-bit number)
The clocks for both shift register 1 and shift register 2 have a low and high time of 5.
As can be seen on the circuit diagram, the output of Q7 (i.e., reg1 MSB signal line) is connected to SI for shift register 1 so that once something is shifted out it is then shifted back in to the LSB of shift register 1. The output of Q7 (reg1 MSB signal line) is also connected to SI for shift register 2 so that the 8-bit number can be received in the reverse order for shift register 2 (i.e., the first bit shifted out of shift register 1 goes to the LSB of shift register 2 and so on and so forth).
The waveform for the reg1 MSB signal line is correct, as when the parallel code is first loaded it has a value of 1, then after the first shift it has a value of 0 (and the 1 that was the MSB is shifted out and then goes to the LSB), and then after the second shift it has a value of 1, and so on and so forth, following the code sequence of 10110101, as it should. However, the waveform for the reg2 MSB signal line is not producing the correct result (i.e.,10101101), but I am not sure why this is the case. I felt like the way I designed the circuit is the logical (and correct) way to go about designing this circuit, so if there are any noticeable issues/problems with my design that would explain why I am getting incorrect results for the reg2 MSB signal line, I would certainly appreciate it if they could be brought to my attention, as I am fairly new to designing circuits.