Is this logic feasible in FPGA?

Dear Reader,

I want to build a logic in my board. It needs to be implemented in FPGA. I don't know abc of FPGA so I would get it done this. But before outsoursing, I need to check the feaibility of the same. It would be great if somebody of you comment on this.

There is FPGA to which a input is a square wave of 16Mz. After deviding it by 524288 (32768 X 16) times the final frequency would be around 30Hz. There is a trigger input (asynchronous) to the FPGA. After getting this trigger, from the next rising edge of 16Mhz clock, it should start deviding the clock to give 30Hz at the output.

So in nut shell,
1. In the absence of trigger I would get 30Hz at the output.
2. After trigger, irrespective of phase of 30Hz, my square wave starts afresh from very next 16MHz clock edge; so the resolution of phase correction is 1/16Mhz i.e. 62.5 ns.

Is it feasible? Or VLSI designer would laught at me?

An FPGA is overkill for that project, but it could be done.

You mention "build... FPGA..your board", and outsourcing, so I guess I'm confused as to who would write the code and build the unit. Is this part of a larger system where an FPGA is already in use and has spare cells and I/O?

Thanks thatoneguy for reply.

Actually, a FPGA will be used for other logic also. I am not the xpert in HDL coding; so I will get it done from third party. Long back I studied this subjet in my college not forgoten everything.

I am wondering if there is any other option to do this.

If you have spare cells in an FPGA, then adding that function wouldn't be a biggie. If it is independent, a PAL (smaller programmable logic, 18-28 pin), or a PLL/Crystal clock Divider would work.