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Old 02-15-2009, 05:29 AM
Skeebopstop Skeebopstop is offline
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Default SCR latchup

Can anyone provide a bit of insight into what is detailed in the following attachment.

I realize that the Vs terminal is being inductively driven below common of the IC but do not fully comprehend the statement of SCR latch up/down.

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File Type: jpg SCR.JPG (178.7 KB, 16 views)
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Old 02-15-2009, 03:07 PM
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beenthere beenthere is offline
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Try this - http://search.microchip.com/searchap...e.aspx?q=an763
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Last edited by beenthere; 02-15-2009 at 03:13 PM. Reason: bad link
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Old 02-15-2009, 05:51 PM
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Ron H Ron H is offline
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There are parasitic (unavoidable) NPNs and PNPs on the output driver of a CMOS chip which are connected in a positive feedback loop that resembles an SCR. If the output swings too far below ground, or too far above the positive supply, the SCR can be triggered, latching up and causing destructive current to flow.
http://www.irf.com/technical-info/designtp/dt94-9.pdf
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Old 02-15-2009, 08:19 PM
Skeebopstop Skeebopstop is offline
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Thanks guys.
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